• Samsung Electronics and AMD signed a memorandum on 18 March 2026 covering primary HBM4 supply for AMD Instinct MI455X and advanced DRAM and DDR5 work for AMD EPYC Venice and AMD Helios.
  • The same announcement says the companies will only discuss opportunities for a foundry partnership. It discloses no fabrication award, node, AMD product, purchase order, volume, allocation, delivery schedule or production start.

The memory scope is specific

The agreement was signed at Samsung’s Pyeongtaek complex with AMD chief executive Lisa Su and Samsung Electronics chief executive Young Hyun Jun present. The companies said they would align on primary HBM4 supply for the AMD Instinct MI455X accelerator and advanced DRAM for sixth-generation AMD EPYC processors, codenamed Venice.

They also plan high-performance DDR5 memory optimized for Venice and systems built on the AMD Helios rack-scale architecture. That is more concrete than the old article’s generic claim of developing AI memory: it identifies the memory generations, the accelerator, the CPU generation and the rack platform.

Foundry work remains an option, not an award

The announcement uses a different commitment level for manufacturing: Samsung and AMD will only discuss opportunities through which Samsung could provide foundry services for future AMD products. It names no process node, product, wafer commitment, packaging allocation, purchase order, qualification milestone, delivery date or production start.

The previous text went beyond that evidence by suggesting AMD might add Samsung alongside existing manufacturing partners and obtain diversification or supply resilience. The memorandum identifies neither a supplier switch nor an additional source, and it does not say a foundry-yield problem must be solved before a disclosed AMD programme can proceed.

Specifications are claims, not delivered outcomes

Samsung says its HBM4 uses a sixth-generation 10-nanometre-class 1c DRAM process and a 4 nm logic base die, with speeds up to 13 Gbps and maximum bandwidth of 3.3 TB/s. Those are Samsung design specifications and maxima. They are not a shipped MI455X count, a system benchmark, a customer deployment result or measured power efficiency in AMD Helios.

AMD repeated the collaboration in its first-quarter results, including HBM4 for MI455X and advanced DRAM for Venice. That later reference confirms the programme remained part of AMD’s announced roadmap; it still reports no volume, qualification completion, delivery, system availability or realised customer benefit.

The relationship is established; execution is the new test

Samsung and AMD describe nearly two decades of collaboration across graphics, mobile and computing. Samsung was already the primary HBM3E partner for AMD Instinct MI350X and MI355X, so the HBM4 plan extends an existing memory relationship rather than creating the companies’ first AI-chip tie.

The next evidence should be operational: completed memory qualification, contracted and delivered quantities, MI455X and Venice availability, Helios integration data, and any foundry award naming the AMD product and process. Until then, component specifications and strategic intent must remain separate from shipment, performance and customer outcomes.

What to watch

  • HBM4 qualification and committed supply for AMD Instinct MI455X.
  • Contracted volumes, allocations, shipment dates and system availability.
  • DDR5 validation for AMD EPYC Venice and AMD Helios.
  • Independent MI455X and Helios bandwidth, power and reliability results.
  • Any foundry award naming an AMD product, node and production timetable.
  • Evidence that HBM3E continuity converts into HBM4 delivery at scale.

Sources