Summary

  • TSMC's $2 billion interposer agreement with GlobalFoundries prepares a component supply ramp for 2028, not an immediate shipment of AI accelerators.
  • The company has acknowledged some backend supply shortage. The delivery question is when chips, memory, assembly and testing will be ready for the same product.

A delivery date for AI servers can set other decisions in motion: a data-centre build, a power contract, a promise to the next customer. Those commitments need complete accelerators, not just the processing chips inside them. If the remaining manufacturing work falls behind, the buyer may have to rearrange a plan that is already costing money.

TSMC has a concrete answer to one part of that problem: a $2 billion manufacturing agreement with GlobalFoundries, announced on 8 October. It covers silicon interposers, components that help connect chips inside an advanced package. Production at Malta, New York, is expected to start ramping in the first half of 2028. The initial agreement runs for five years.

The component is obscure; the commitment is not. As described in the GlobalFoundries announcement, TSMC is arranging another source for its CoWoS packaging ecosystem years before that source reaches its planned production ramp. Here the chipmaker is the customer, securing work it will need after making the chips.

The agreement is a step towards future supply, rather than a promise of extra finished accelerators this quarter. Following what it buys explains why an AI hardware delivery date depends on more than the capacity of a cutting-edge chip factory.

The work after the wafer

An AI accelerator needs its processing chips and memory to communicate rapidly. Putting them near one another is not enough; the connections have to work at the required density, speed and power consumption. Packaging provides those connections, and the assembly must then pass the relevant production and testing steps.

TSMC's CoWoS technical description makes clear why the word “packaging” understates the job. CoWoS-S uses a silicon interposer. CoWoS-R uses a redistribution layer made of polymer and copper. CoWoS-L combines redistribution wiring with local silicon interconnects and other embedded elements. They belong to one family, but they are not interchangeable units of factory output.

This is why a wafer count cannot simply be relabelled an accelerator count. Package size, design, yield and the mix of products affect what emerges at the other end. A bigger fabrication plant can supply more processing silicon without, by itself, completing any more of these assemblies.

TSMC has acknowledged a constraint here. Near the end of its 15 October earnings call, C.C. Wei described some shortage in backend supply while explaining the GlobalFoundries agreement. That is stronger evidence than an outsider's suspicion. It is not, however, a measurement of how many accelerators are delayed, for which buyers, or for how long.

A very good quarter is not a delivery schedule

The third-quarter results show revenue of $46.72 billion, above the earlier $44.6 billion–$45.8 billion guidance. Gross margin was 66.4% and operating margin 58.7%. For the fourth quarter, the company expects revenue of $52.3 billion–$54.3 billion, gross margin of 65%–67% and operating margin of 56.5%–58.5%.

These figures describe sales and profitability, not the spare room in a packaging line. The distinction survives even a large increase in spending. On the October call, TSMC reiterated a full-year capital budget of $60 billion–$64 billion. The $52 billion–$56 billion range quoted in a July report is earlier guidance, not the current budget. Neither total tells a buyer which package, at which site, will be available on a particular date.

Revenue mix has the same limitation. In the third quarter, 7-nanometre and more advanced processes accounted for 79% of wafer revenue; high-performance computing accounted for 68% of total revenue. Those are different denominators. Neither is a count of completed packages.

A capacity estimate acquires a life of its own

A TechTimes article dated 11 July gives a memorable series: roughly 35,000 CoWoS wafers a month at the end of 2024, 75,000 at the end of 2025 and a target of 125,000–130,000 at the end of 2026. It attributes the numbers to TrendForce.

Following that link changes the picture. The 15 June TrendForce News item cites another newspaper's reporting and gives a different forecast: 120,000–140,000 monthly wafers for TSMC in 2026, plus 50,000–60,000 of capacity from packaging partners. The page also distinguishes its news operation from its research team. It does not reproduce the exact historical series attributed to it in July.

That does not establish which forecast will prove right. It does mean the neat three-number progression should not be presented as a verified company series—or as research whose method has been checked. A planning spreadsheet can preserve the number while losing the distinction between TSMC, its partners and the wider market. The arithmetic may remain flawless while the delivery assumption goes wrong.

A factory on the map is only part of the route

There is more evidence of expansion than an old announcement alone suggests. TSMC's current manufacturing overview says it expanded advanced-packaging capacity in Chiayi and Tainan in 2025. That is a statement about expansion, not merely an intention to build. It still does not supply a site-by-site rate of qualified finished output.

In Japan, the October call places 3-nanometre volume production at the second fab in 2028. The earlier DIGITIMES report of 7 August discusses Kumamoto and a broader Japanese packaging push in its public introduction; its full text requires a subscription. A fabrication schedule does not establish where every resulting chip will be assembled.

The New York interposer agreement addresses another part of that route. It may widen supply options, but a component supplier's future ramp is not proof that every later manufacturing stage is ready. Nor does the location of a wafer fab establish that its products must cross the Pacific: the actual packaging route has to be identified.

What a customer can—and cannot—reserve

Customers do make financial commitments to secure manufacturing capacity. TSMC's 2025 Form 20-F describes advance receipts for specified fab capacity, with refunds or offsets against receivables determined under the agreements. That is not a disclosure of a particular buyer's packaging reservation, cancellation penalty or take-or-pay obligation.

The filing also reports that the largest customer supplied 19% of 2025 revenue, the second-largest 17%, and the top ten 78%. Concentration is measurable. The identity of the customer first in a packaging queue is not revealed by those percentages.

For a server supplier or data-centre developer, the practical question therefore becomes narrower than “Is TSMC expanding?” It plainly is. The question is whether the specific processing chips, memory, packaging and testing needed for a promised delivery are ready together. If they are not, power contracts, construction milestones and customer commitments may become harder to keep. This is a planning exposure, not evidence that a named buyer has suffered a loss.

The interposer is almost invisible in the finished machine. In the schedule, it cannot be.

Source notes

The original Chiayi announcement link is retained, but its text could not be retrieved for this update; the expansion statement above comes from the current company overview. TSMC's annual-report archive and SEC filing index remain useful entry points. The specific customer and advance-receipt disclosures cited here are in the company-hosted 2025 filing, rather than inferred from those indexes.