Intelligence
Latest Articles
Latest intelligence on infrastructure operators, policy decisions, market moves, and digital power shifts.
Creators
Sage Weil: the engineer who made distributed storage computable
Sage Weil’s most enduring contribution was not a storage device but an architecture. CRUSH calculates data placement, while RADOS distributes storage, repair and movement across the cluster. Ceph enabled ordinary machines to operate as one system, then had to learn to continue…
Creators
Sage Weil: The Architect Who Made Distributed Storage Calculable
Sage Weil’s most durable contribution to internet infrastructure was not a storage appliance but an architecture. Ceph used CRUSH to calculate where data belongs and RADOS to spread storage, repair and movement across a cluster. The design helped commodity machines behave like…
Global Institutional
NVM Express: how storage became a network protocol
NVMe began as a more efficient way to talk to the flash memory installed in a server. It has become a family of protocols capable of carrying the same command queues and namespaces over PCIe, TCP or RDMA. That continuity has made storage composable, while moving part of its…
Global Institutional
NVM Express: how storage became a network protocol
NVMe began as a more efficient way to communicate with flash memory installed inside a server. It became a family of protocols capable of carrying the same queue, controller and namespace model over PCIe, TCP or RDMA. That continuity enabled capacity to be disaggregated, but…
Global Institutional
NVM Express: How storage became a network protocol
NVMe began as a more efficient language for flash storage in the server. It became a protocol family that carries the same model of queues, controllers and namespaces over PCIe, TCP or RDMA. That continuity made storage composable but shifted complexity into the fabric, firmware…
Global Institutional
The UCIe promise for chiplets depends on what lies beyond the link
UCIe has defined a die-to-die interface that reaches 64 GT/s and now spans 3D packaging, raw traffic and whole-package management. The decisive test will be whether these rules sustain multi-vendor products when power, thermals, manufacturing yield, software, security and…
Global Institutional
NVM Express: How storage became a network protocol
NVMe began as a more efficient protocol for accessing flash inside servers and developed into a family of standards that carries consistent queue, controller and namespace semantics over PCIe, TCP and RDMA. It makes storage easier to pool and compose while shifting complexity…
Global Institutional
NVM Express: How Drives Became a Network Protocol
NVMe began as a queue architecture for flash drives attached over PCI Express. Over time it grew into a modular protocol family that can reach storage over TCP and RDMA networks, supports resource discovery and multiple paths, describes specialised storage media models and…
Global Institutional
UCIe's chiplet promise depends on engineering and accountability beyond the link
UCIe has pushed the die-to-die interface to 64 GT/s and added 3D packaging, raw data transport and whole-package management. The real test is whether these rules can support multi-vendor products when power delivery, thermals, yield, software, security and accountability still…
Global Institutional
UCIe’s chiplet promise will be decided beyond the link
UCIe now defines a die-to-die interface reaching 64 GT/s and covering 3D packaging, raw traffic and package-wide management. Its market value depends on whether these rules can support multi-vendor products while power, thermal design, yield, software, security and liability…
Global Institutional
UCIe’s chiplet vision will be decided beyond the link
UCIe defines die-to-die links reaching 64 GT/s and now covers 3D packaging, raw traffic and package-wide management. Its real test is whether multi-vendor products can succeed while power, heat, yield, software, security and responsibility remain outside the standard.
Global Institutional
UCIe’s chiplet promise extends beyond the link
UCIe has defined a die-to-die interface capable of 64 GT/s, 3D stacking, raw traffic and package-wide management. The decisive test is whether those rules enable multi-vendor products while power, thermal design, manufacturing yield, software, security and contractual…
Global Institutional
The promise of UCIe depends on what happens beyond the link
UCIe has defined an inter-chip interface that reaches 64 GT/s and already covers 3D packaging, raw traffic and whole-package management. The decisive test will be whether those rules can sustain multi-vendor products when power, thermals, manufacturing yield, software, security…
Global Institutional
UCIe's chiplet promise hinges on what lies beyond the link
UCIe has defined a die-to-die interface that reaches 64 GT/s and now covers 3D packaging, raw data traffic and package-wide management. The deciding question is whether these rules can support multi-vendor products when power delivery, thermals, manufacturing yield, software…
Global Institutional
UCIe’s chiplet promise depends on more than the link
UCIe has defined a die-to-die interface reaching 64 GT/s and expanded its scope to 3D packaging, raw data traffic and whole-package management. The decisive test is whether these rules can support multi-vendor products while power, thermal design, manufacturing yield, software…
Global Institutional
UCIe’s chiplet promise depends on what happens beyond the link
UCIe has defined a die-to-die interface that reaches 64 GT/s and now covers 3D packaging, raw traffic and package-wide management. The consortium’s real test is whether those rules can support multi-vendor products when power, thermal design, yield, software, security and…
History
Vint Cerf Before the Cutover: Why TCP/IP Needed a Network
The decisive work behind TCP/IP was not a single flash of invention. It was a decade of drawing, challenging and implementing boundaries: between networks and hosts, datagrams and reliable conversations, design authority and operational responsibility. Vint Cerf was a visible…
Global Institutional
PCI-SIG: The common rules inside AI servers
An AI server may combine processors, accelerators, network cards, storage controllers, switches, retimers and security devices from competing vendors. PCI-SIG maintains a common interface that lets these components be discovered, negotiate capabilities and exchange data, while…
Global Institutional
PCI-SIG and the rulebook inside the AI server
An AI server can bring together processors, accelerators, network cards, storage controllers, switches, retimers and security devices from competing companies. PCI-SIG maintains the common interface that lets these parts meet and exchange data, and runs the test programmes used…
Global Institutional
PCI-SIG: The common rules that power AI servers
PCI-SIG sets the common rules that let AI server components work together and backs them with compliance testing. Its authority is limited to connectivity layer.