Summary

  • NVM Express, Inc. is the non-profit industry alliance that manages the NVMe family of specifications. It does not manufacture SSDs, controllers, switches or storage arrays.
  • NVMe replaces the narrower, more serial queue model of the hard-drive era with multiple in-memory submission and completion queues, making it better suited to parallel flash storage and multicore processors.
  • The same controller, subsystem and namespace semantics can operate inside a server over PCIe or provide services across TCP or RDMA networks through NVMe over Fabrics.
  • NVMe 2.x uses a modular architecture. The 2.4 specification set made public on 4 August 2026 includes Base, PCIe/RDMA/TCP transports, NVMe-MI, Boot and several specialised command sets.
  • The protocol makes capacity more composable, but it does not define filesystems, durability, RAID, erasure coding, network design, operational security or application consistency.

Storage commands can leave the server without changing their basic language

A read request can be sent to a namespace on a local PCIe SSD or across a fabric to a remote subsystem. The media, controller and path change, while the command, queue and namespace model remains broadly consistent.

This is the basis of storage disaggregation. Capacity can be concentrated in shared pools and allocated to hosts as required, without installing every drive in the chassis that uses it.

Leaving the server, however, introduces discovery, networking, multipath, authentication, reconnection and new failure domains. NVMe makes storage a programmable service; it does not make topology disappear.

Flash requires a protocol designed for parallelism

Traditional storage interfaces were shaped by mechanical seeks and relatively few concurrent operations. Flash can process many requests simultaneously, while modern servers have numerous CPU cores.

NVMe uses in-memory submission and completion queues. The host writes a command, notifies the controller through a doorbell, then reads the completion through an interrupt or polling. Multiple queues can be assigned to different cores or processes, reducing shared locks and contention.

Actual results still depend on controller firmware, PCIe topology, NUMA, queue depth, interrupt policy and workload. Adopting NVMe does not automatically deliver a fixed level of performance.

The alliance separates protocol governance from product competition

Work on NVMe began in the late 2000s, the 1.0 specification was released in 2011, and NVM Express, Inc. was established in 2014. Alliance members come from the processor, flash, controller, networking, systems and cloud-computing industries.

At the research cut-off, Google’s Amber Huffman served as President, AMD’s Curtis Ballard as Treasurer and Microchip’s David Allen as Secretary; the public board listed 13 promoter representatives.

The alliance manages the contract, changes and compliance framework, while members continue to compete on chips, firmware, system design, support and performance. Participation in standards work does not mean that a product implements every feature.

NVMe 2.0 split an expanding single document into a modular family

As transports beyond PCIe and new data models emerged, maintaining everything in one specification became increasingly difficult. The NVMe 2.0 restructuring in 2021 separated Base, command sets and transports.

This allows the TCP transport to evolve independently and Zoned Namespace to expand without requiring changes to every conventional controller. The trade-off is that buyers must manage more complex combinations of versions.

The NVMe 2.4 set made public on 4 August 2026 includes Base 2.4, PCIe Transport 1.4, RDMA Transport 1.3, TCP Transport 1.3, NVMe-MI 2.2, Boot 1.4, and command sets including NVM, Key Value, Zoned Namespace, Computational Programs and Simple Log Memory. “NVMe 2.4” is not a single document.

Submission and completion queues bring storage work closer to CPU cores

The host writes commands to a submission queue, and the controller writes results to a completion queue. Different cores or applications can use separate queue pairs, reducing global locks and context switching.

Doorbells signal new work. Polling can reduce some latency but continuously consumes CPU resources; interrupt coalescing saves CPU resources but can increase waiting time. Queue depth affects utilisation and tail latency.

Deeper queues are not always better. They can conceal saturation and lengthen queuing time. Correct configuration must start with the workload and service-level agreement.

Controllers, subsystems and namespaces separate logical endpoints from physical media

A controller exposes queues and commands. A subsystem can contain multiple controllers. A namespace represents logical capacity and can be presented to a host through different controllers and paths.

The identity seen by the host therefore does not have to correspond to one physical SSD. An array can combine different media while providing a stable namespace.

NVMe does not determine how data is placed, replicated or protected. RAID, erasure coding, thin provisioning, snapshots and application consistency remain the responsibility of higher-level systems.

Administrative commands are as important as ordinary I/O

The administrative queue is used to identify devices, create I/O queues, configure features, read logs, and manage firmware, namespaces and security. It controls the environment in which ordinary reads and writes can occur.

An incorrect administrative command can delete a namespace, activate the wrong firmware or change a power state. Permissions, auditing and change control must cover this layer.

Separating administration from I/O benefits the architecture, but it does not make the control plane secondary. In a fabric, both can sometimes depend on the same network and identity system.

PCIe keeps the local path close to memory and hardware

NVMe over PCIe communicates with controller registers through shared-memory structures on the local bus, providing a direct path to SSDs and cards inside a server.

Physical proximity does not mean simple topology. A device may sit behind a PCIe switch, connect to another NUMA socket or share lanes. The positions of the CPU, memory and device affect performance.

Drive counts alone are therefore limited public evidence. Abnormal latency can originate in the host’s internal PCIe path before a request reaches the media.

NVMe over Fabrics turns a local controller relationship into a network service

NVMe-oF 1.0 and NVMe-MI 1.0 were released on 9 June 2016. NVMe-oF carries command capsules and data to a remote subsystem, with the host establishing queues across the fabric and accessing namespaces.

This enables capacity pooling and the separation of compute from storage. Hosts can be replaced while data remains in the shared system.

At the same time, NICs, switches, routes, discovery, controllers, authentication and multipath enter the data path. The network is no longer merely a connection; it becomes part of storage integrity.

Discovery controllers simplify dynamic access but also create a critical dependency

A host can query a discovery controller to obtain available subsystems, addresses and services. This avoids manually configuring paths for every target and makes it easier to add or remove resources dynamically.

Incorrect information or a discovery-service outage can prevent new connections or direct hosts to the wrong target. Redundancy, caching, identity protection and content validation are required.

Discovery availability differs from data-path availability. Existing sessions may continue working even when new hosts cannot discover the service.

NVMe/TCP brings fabric storage to conventional IP networks

Standardised in 2019, NVMe/TCP maps commands and data to TCP connections. Operators can use routable Ethernet, IP tools, firewalls and familiar network practices without building an RDMA fabric.

Convenience comes with overhead. The TCP stack, copying, interrupts and CPU use can affect tail latency. Kernel implementation, offload, transfer size and tuning all matter.

The transport also defines storage-specific framing and digests and can use TLS. Support for TLS does not mean it has been enabled or is being operated securely.

NVMe/RDMA pursues low latency while demanding stricter fabric engineering

RDMA reduces CPU involvement through queue pairs, registered memory and NIC offload, making it suitable for HPC and AI settings where microseconds and CPU cycles matter.

RDMA is not a single uniform network. Bindings such as RoCE and iWARP have different requirements for congestion, packet loss, PFC, ECN and memory management.

A low-latency benchmark does not imply simple operations. Network faults can appear as storage timeouts and require network and systems teams to diagnose them together.

Multipath turns redundancy into a host policy choice

A namespace can be accessed through multiple controllers and paths. The host determines load balancing and failover. Asymmetric Namespace Access marks paths as optimised, non-optimised or unavailable.

Two links may still share a switch, controller, power supply or route. Genuine independence must be verified through failure testing.

An incorrect policy may retain a bad path for too long or send I/O over a slower path. Redundancy should be measured by actual behaviour, not port count.

Reservations coordinate shared access but cannot replace cluster consensus

NVMe reservations allow hosts to register with and reserve a namespace, preventing access by unauthorised writers. They are commonly used for clusters and failover.

They do not replace consensus protocols or application consistency. A failed host can leave reservation state behind, and recovery must fence the old node to prevent it from writing again.

Incorrect recovery can turn a protection mechanism into a source of unavailability or data corruption.

Once storage leaves PCIe, authentication and TLS become necessary

Local devices often inherit a physical boundary. After they are connected over a network, initiators and targets need to prove their identities and protect the appropriate control and data channels.

NVMe defines authentication mechanisms, and NVMe/TCP can use TLS. Actual protection depends on keys, certificates, rotation, algorithms, access policies and implementation quality. The presence of a feature does not mean secure configuration is complete.

Discovery, administrative and data planes must be assessed together. An authentic identity can still have excessively broad permissions.

NVMe-MI provides a management path independent of application I/O

The NVMe Management Interface allows tools to discover subsystems, read health status, inventory devices and perform certain management actions even when the primary I/O path is not being used by an application.

This supports maintenance and recovery but introduces another privileged interface. A central management platform can read sensitive information or change devices in bulk.

NVMe-MI can integrate with management systems such as Redfish. Integration does not merge the responsibilities of different standards organisations and suppliers.

Zoned Namespace exposes media constraints to host software

ZNS divides capacity into sequentially written zones. When software understands the media layout, it may reduce garbage collection inside the controller and improve endurance or predictability.

These benefits require the filesystem, database or storage layer to understand zones. Applications designed for a conventional block device do not gain the advantages automatically.

ZNS illustrates an NVMe trade-off: exposing more media behaviour can improve efficiency while increasing the software portability cost.

Key Value, Simple Log Memory and Computational Programs extend the meaning of a namespace

Specialised command sets support key/value access, simple log memory or the execution of programs near storage, with the aim of reducing translation and data movement.

Adoption depends on controllers, drivers, libraries and applications. Inclusion in a specification does not mean that every SSD and array provides the feature.

As the number of features grows, capability discovery and fallback become more important. Modularity provides flexibility while creating new commercial compatibility matrices.

Compliance provides useful evidence but does not certify end-to-end performance

Compliance programmes and interoperability workshops test specific host-controller behaviour and can reveal discrepancies that are not apparent from reading the specification alone.

Being listed does not guarantee a particular level of latency, endurance, recovery or security in every topology. Optional features and driver-firmware matrices continue to change.

Buyers should treat compliance as a baseline and test their own workloads, failures and upgrade procedures.

Storage disaggregation separates capacity from servers and redistributes responsibility

Local storage often binds the device, host and systems team together. A remote pool can serve multiple consumers and have its allocation adjusted through software.

Network, storage, platform, security and application teams consequently share the same incident. Fabric degradation can resemble a database problem, while a controller-firmware problem can resemble network loss.

The economic benefit depends on capacity utilisation and operational capability, not merely the price per terabyte.

AI turns storage latency directly into compute cost

Training jobs must load datasets, write checkpoints and exchange large amounts of state. When thousands of accelerators are waiting, storage tail latency wastes expensive computing resources.

TCP, RDMA, multipath and shared namespaces offer different architectures. Selection must account for congestion, metadata, queue behaviour, faults and recovery.

The objective should not be peak throughput alone, but predictable queuing and recovery times under synchronised workloads.

NVMe 2.4 demonstrates the protocol’s scope while increasing version pressure

The 2.4 set coordinates Base, transports, Boot, the Management Interface and specialised command sets. NVMe has become a complete stack rather than merely an SSD interface.

A host can support Base 2.4 without supporting every command set, and a TCP controller may have different capabilities from an RDMA product. Support claims must be specific.

In practice, the matrix formed by drivers, operating systems, firmware, transports and management tools is part of the protocol.

NVMe makes storage composable, but it does not make the service simple

A common protocol reduces one switching cost: commands and namespaces can move from PCIe to a fabric or from one supplier to another. Data migration, identity, security, networking, observability and support costs remain.

The advantage is a clearer separation between protocol and product. The risk is that the name “NVMe” conceals markedly different architectures.

Storage therefore becomes more programmable and distributable, but it remains a data-integrity system whose behaviour under failure must be clearly understood.