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Latest intelligence on infrastructure operators, policy decisions, market moves, and digital power shifts.

AI生成编辑插图,展示NVMe SSD服务器、网络交换机与数据中心存储节点互联,代表NVMe over Fabrics架构

Global Institutional

NVM Express: How storage became a network protocol

NVMe began as a more efficient protocol for accessing flash inside servers and developed into a family of standards that carries consistent queue, controller and namespace semantics over PCIe, TCP and RDMA. It makes storage easier to pool and compose while shifting complexity…

Aug 19, 2026
NVM Express: How Drives Became a Network Protocol

Global Institutional

NVM Express: How Drives Became a Network Protocol

NVMe began as a queue architecture for flash drives attached over PCI Express. Over time it grew into a modular protocol family that can reach storage over TCP and RDMA networks, supports resource discovery and multiple paths, describes specialised storage media models and…

Aug 19, 2026
展示 UCIe 芯粒互连架构的 AI 生成编辑插图,CPU、内存、加速器、安全和模拟模块通过发光的裸片间链路连接

Global Institutional

UCIe's chiplet promise depends on engineering and accountability beyond the link

UCIe has pushed the die-to-die interface to 64 GT/s and added 3D packaging, raw data transport and whole-package management. The real test is whether these rules can support multi-vendor products when power delivery, thermals, yield, software, security and accountability still…

Aug 19, 2026
UCIe’s chiplet promise will be decided beyond the link

Global Institutional

UCIe’s chiplet promise will be decided beyond the link

UCIe now defines a die-to-die interface reaching 64 GT/s and covering 3D packaging, raw traffic and package-wide management. Its market value depends on whether these rules can support multi-vendor products while power, thermal design, yield, software, security and liability…

Aug 19, 2026
UCIe’s chiplet vision will be decided beyond the link

Global Institutional

UCIe’s chiplet vision will be decided beyond the link

UCIe defines die-to-die links reaching 64 GT/s and now covers 3D packaging, raw traffic and package-wide management. Its real test is whether multi-vendor products can succeed while power, heat, yield, software, security and responsibility remain outside the standard.

Aug 19, 2026
Illustration éditoriale de chiplets de calcul, mémoire, accélération, I/O et sécurité reliés par UCIe dans un boîtier avancé.

Global Institutional

UCIe’s chiplet promise extends beyond the link

UCIe has defined a die-to-die interface capable of 64 GT/s, 3D stacking, raw traffic and package-wide management. The decisive test is whether those rules enable multi-vendor products while power, thermal design, manufacturing yield, software, security and contractual…

Aug 19, 2026
Ilustración editorial de chiplets de CPU, memoria, acelerador, I/O y seguridad conectados mediante UCIe dentro de un encapsulado avanzado.

Global Institutional

The promise of UCIe depends on what happens beyond the link

UCIe has defined an inter-chip interface that reaches 64 GT/s and already covers 3D packaging, raw traffic and whole-package management. The decisive test will be whether those rules can sustain multi-vendor products when power, thermals, manufacturing yield, software, security…

Aug 19, 2026
UCIe's chiplet promise hinges on what lies beyond the link

Global Institutional

UCIe's chiplet promise hinges on what lies beyond the link

UCIe has defined a die-to-die interface that reaches 64 GT/s and now covers 3D packaging, raw data traffic and package-wide management. The deciding question is whether these rules can support multi-vendor products when power delivery, thermals, manufacturing yield, software…

Aug 19, 2026
UCIe’s chiplet promise depends on more than the link

Global Institutional

UCIe’s chiplet promise depends on more than the link

UCIe has defined a die-to-die interface reaching 64 GT/s and expanded its scope to 3D packaging, raw data traffic and whole-package management. The decisive test is whether these rules can support multi-vendor products while power, thermal design, manufacturing yield, software…

Aug 19, 2026
Editorial illustration of a UCIe die-to-die interconnect linking CPU, memory, accelerator, I/O, security and analogue chiplets inside an advanced semiconductor package.

Global Institutional

UCIe’s chiplet promise depends on what happens beyond the link

UCIe has defined a die-to-die interface that reaches 64 GT/s and now covers 3D packaging, raw traffic and package-wide management. The consortium’s real test is whether those rules can support multi-vendor products when power, thermal design, yield, software, security and…

Aug 19, 2026
AI-assisted editorial portrait of Vint Cerf, grounded in a licensed 2005 photograph, beside an abstract network layer.

History

Vint Cerf Before the Cutover: Why TCP/IP Needed a Network

The decisive work behind TCP/IP was not a single flash of invention. It was a decade of drawing, challenging and implementing boundaries: between networks and hosts, datagrams and reliable conversations, design authority and operational responsibility. Vint Cerf was a visible…

Aug 19, 2026
展示 PCI-SIG 与 PCI Express 如何连接 AI 服务器内部处理器、加速器、网络和存储组件的编辑插图。

Global Institutional

PCI-SIG: The common rules inside AI servers

An AI server may combine processors, accelerators, network cards, storage controllers, switches, retimers and security devices from competing vendors. PCI-SIG maintains a common interface that lets these components be discovered, negotiate capabilities and exchange data, while…

Aug 18, 2026
PCI-SIG and the rulebook inside the AI server

Global Institutional

PCI-SIG and the rulebook inside the AI server

An AI server can bring together processors, accelerators, network cards, storage controllers, switches, retimers and security devices from competing companies. PCI-SIG maintains the common interface that lets these parts meet and exchange data, and runs the test programmes used…

Aug 18, 2026
PCI-SIG: The common rules that power AI servers

Global Institutional

PCI-SIG: The common rules that power AI servers

PCI-SIG sets the common rules that let AI server components work together and backs them with compliance testing. Its authority is limited to connectivity layer.

Aug 18, 2026
Illustration éditoriale de PCI-SIG et des connexions PCI Express reliant les composants d’un serveur moderne d’intelligence artificielle.

Global Institutional

PCI-SIG: the internal rulebook of the AI server

An AI server can bring together processors, accelerators, network cards, storage controllers, switches, retimers and security devices from competing companies. PCI-SIG maintains the common interface that lets these components discover one another and exchange data, then organises…

Aug 18, 2026
Ilustración editorial de PCI-SIG y conexiones PCI Express entre componentes de un servidor moderno de inteligencia artificial.

Global Institutional

PCI-SIG and the internal rules of the AI server

An AI server can bring together processors, accelerators, network adapters, storage controllers, switches, retimers and security devices from companies that compete with one another. PCI-SIG maintains the common interface that lets these components discover one another and…

Aug 18, 2026
PCI-SIG and the rulebook in the AI server

Global Institutional

PCI-SIG and the rulebook in the AI server

An AI server can combine processors, accelerators, network cards, storage controllers, switches, retimers and security devices from companies that otherwise compete with one another. PCI-SIG maintains the common interface through which these components discover each other and…

Aug 18, 2026
PCI-SIG and the interconnect rules inside AI servers

Global Institutional

PCI-SIG and the interconnect rules inside AI servers

An AI server may combine processors, accelerators, network cards, storage controllers, switches, retimers and security devices from companies that compete elsewhere. PCI-SIG maintains the shared interface that allows these components to recognise one another, negotiate…

Aug 18, 2026
PCI-SIG and the rules that make an AI server work

Global Institutional

PCI-SIG and the rules that make an AI server work

A single AI server can contain processors, accelerators, network adapters, storage controllers, switches, retimers and security components from companies that compete everywhere else. PCI-SIG maintains the common interface that lets these components find and talk to each other…

Aug 18, 2026
PCI-SIG branding above a PCIe connector in a high-speed data-centre environment

Global Institutional

PCI-SIG and the rulebook inside the AI server

An AI server may bring together processors, accelerators, network adapters, storage controllers, switches, retimers and security devices from companies that compete everywhere else. PCI-SIG maintains the shared interface that lets those parts find one another and exchange data…

Aug 18, 2026