Summary

  • PCI-SIG is a non-profit, member-led standards organisation founded in 1992 around the Peripheral Component Interconnect standard. Today it maintains the PCI Express family, electromechanical and form-factor documents, security extensions, compliance workshops, authorised test labs, the Integrators List and brand rules.
  • PCI Express went from being the serial successor to a personal-computer expansion bus to a fabric used in servers, storage, network devices and AI platforms with many accelerators. PCIe 6.0 introduced 64 GT/s, PAM4 and fixed FLITs; PCIe 7.0 reached 128 GT/s in June 2025; PCIe 8.0 Draft 0.5, distributed to members in May 2026, targets 256 GT/s and up to 1 TB/s bidirectional on x16 for 2028.
  • The headline figures are raw interface targets, not application-performance promises. The outcome depends on negotiated width and speed, protocol overhead, switches, retimers, firmware, connectors, boards, power, cooling and workload behaviour.
  • PCI-SIG can publish common rules and test defined configurations, but it does not guarantee that every listed product works with every server, does not certify all firmware, does not govern CXL or UCIe and does not decide the use of proprietary fabrics or Ethernet. Its achievement is the controlled evolution of a multi-vendor connection layer, not total control of the AI system.

A server only becomes a market when its components share a link

An acceleration server looks like a single product. Inside, it brings together several industries: CPUs, GPUs or specialised accelerators, network adapters, storage, switches, retimers, cables and security devices. Each part can be excellent on its own and commercially useless if the host and the peripheral cannot find each other, negotiate capabilities, exchange transactions and recover from errors predictably.

PCI Express provides much of that common language. It does not tell a GPU how to run a model or a storage drive how to organise data; it defines the electrical and protocol conditions that make communication possible. That interface turns a one-off integration into a market, because vendors can design against a shared platform instead of negotiating a private connection for every buyer.

PCI-SIG governs the connection layer, not the whole machine

The PCIe layer is central, but not complete. PCI-SIG does not design the processor package, operating system, memory coherence or chassis cooling. CXL adds memory and cache semantics on PCIe foundations. UCIe addresses links between dies inside a package. NVMe defines how storage uses PCIe. Manufacturers also use proprietary fabrics for certain accelerator-to-accelerator relationships.

This division is not a weakness; it is the normal way to build infrastructure. A compliant accelerator can still fail because of BIOS, driver, firmware, retimer, power or temperature. PCI-SIG creates a rulebook at a decisive boundary; platform vendors and operators remain responsible for the complete system.

The organisation was born from the practical need for a common peripheral bus

PCI-SIG traces its origins to 1992, when the industry needed a common interface for expansion cards and motherboard devices. A shared parallel bus reduced the number of proprietary solutions and allowed card makers to serve more than one system builder.

The first PCI ecosystem established a principle that still holds: interoperability requires more than a public pinout. Configuration, timing, software discovery, error management and mechanical form must all match. The standard did not eliminate drivers or platform qualification, but it reduced the number of assumptions negotiated in private.

The move from parallel PCI to serial PCI Express changed the interface's scale

A parallel bus shares many wires and a clock signal among several devices. As frequency rises, aligning signals, controlling noise, limiting pins and dividing bandwidth becomes difficult. PCI Express replaced that model with differential serial lanes, point-to-point links and packetised transactions.

The change turned expansion into a small network inside the machine. Links train, negotiate width and speed, carry packets and report errors. Switches connect multiple endpoints. That flexibility took PCIe far beyond the desktop graphics card: server storage, appliances, embedded systems and accelerator fabrics.

The layered architecture allows the signalling to change without rewriting the whole software model

PCI Express separates the Transaction, Data Link and Physical layers. Reads, writes and messages visible to software live in the transaction layer; reliable link delivery is managed further down; the physical layer controls lanes, training and signalling.

This separation makes it possible to change the electricals without requiring every operating system to learn a new device model. The boundaries are not waterproof. A physical failure can appear as a protocol retry, a firmware timeout or an application crash. The architecture reduces the scope of each change; it does not remove the need to test the layers together.

Backward compatibility turned every upgrade into a negotiation rather than a break

New generations allow a modern host and an older device to agree on a common speed and width. The policy protects the installed base and helps introduce a generation without replacing every peripheral.

Compatibility does not guarantee the advertised performance. A device may run at an older generation or with fewer lanes because of a connector, retimer, trace or legacy limitation. The link is operational, but not necessarily at its target. The difference between 'it appeared' and 'it performs as designed' concentrates many integration problems.

A non-profit body controls a private rulebook of widespread use

PCI-SIG is not a state regulator or a manufacturer. It is a non-profit corporation governed by a board elected by its members. More than a thousand companies from processors, systems, storage, networking, connectors, testing and software take part in the ecosystem. Membership gives access to drafts, review, technical groups and compliance programmes.

The private authority is tangible. Early access influences design schedules; brand rules discipline compatibility promises; testing provides purchasing signals. The authority is strong over documents and trademarks, weaker over implementation quality and indirect over deployed platforms.

Technical groups spread authorship even though the public leadership is easy to identify

The chair, executive staff and board provide recognisable faces. Technical content is produced in groups with electrical specialists, protocol architects, form-factor teams, security, compliance and test vendors. Their agreements determine what can be built and measured years later.

Public biographies do not show who drafted each clause or resolved each dispute. PCIe generations are collective institutional products, not inventions of one executive or one company. Technical continuity depends on the depth of the groups, the documentation and the ability of companies to retain experienced engineers.

Enduring leadership gives PCI-SIG memory between generations

Al Yanes has been president since 2003 and chair since 2006. Reen Presnell has been executive director since 2007, after supporting the organisation since 2000. That continuity covers the period in which PCIe went from initial adoption to being the dominant interface of modern servers.

Long tenure preserves knowledge about trade-offs, compliance failures and design rationale. It can also concentrate informal influence and makes succession important. The public record shows offices and board, but not the full distribution of authorship, voting and internal negotiation.

A thousand members broaden the evidence without distributing influence equally

A connector maker sees channel loss differently from a CPU designer. Storage cares about hot-plug; the accelerator about fan-out and latency; the test provider about measurable ambiguities. Diversity improves the rulebook.

It does not remove inequality of resources. A large company can assign several engineers, build early silicon and pay for many iterations. A small one can access drafts without following every meeting. Member governance avoids a single owner, but it does not demonstrate equal influence.

Draft access makes membership part of the development economy

Generations are designed while SerDes, controllers, packages, connectors and tools are still under construction. Successive revisions allow implementers to find problems before the final version.

Membership provides access to a target that is still moving and a formal channel for feedback. Non-members can use summaries and, later, available documents, but they have less ability to change a decision before silicon makes change expensive. The model funds and organises the standard, while making early access depend on institutional participation.

Changing a specification is a phased negotiation, not a product launch

A generation goes through objectives, early drafts, review drafts and final publication. Separate groups handle protocol, electricals, CEM, cables, security and testing. Broad objectives become decisions about encoding, latency, states, connectors and measurement methods.

That is why an announcement is not maturity. PCIe 8.0 Draft 0.5 is the first official draft for members, not a finished standard or a commercial ecosystem. Connectors, FEC, reliability, power consumption and protocol details can still change before 2028.

Engineering Change Notices let a published generation evolve explicitly

A specification does not stand still once published. PCI-SIG uses Engineering Change Notices, or ECNs, to add capabilities, clarify requirements and correct areas that need an extension between generations. That matters because silicon, firmware and test equipment advance on different schedules.

ECNs also complicate the word 'compatible'. Two products of the same generation can implement different notices, options or errata. The buyer needs the exact revision applied and tested. PCI-SIG provides a disciplined path for changing the rule; manufacturers, labs and operators must record which version exists in each product.

The Base Specification is only one part of a working PCIe system

The Base Specification defines transactions, training, flow control and errors. It is the common grammar, but it is not enough to build a server. Electromechanical rules, form factors, cables, security and compliance must also match.

A product can meet one layer and fail another. PCIe is a coordinated family of documents. The institutional work is to keep electrical, mechanical, firmware, software and test interfaces aligned while different markets use them in different ways.

Enumeration is the silent contract that lets firmware and the system find devices

Before moving data, the platform must discover the accelerator, allocate address space, configure interrupts and expose capabilities. PCIe maintains a configuration model for enumerating endpoints, bridges and switches.

Responsibility is shared. The device announces capabilities, firmware allocates resources, platform code configures the topology and the operating system loads the driver. A defect in any step can hide compliant hardware. The standard provides the language; BIOS, operating systems and vendors must implement it consistently.

CEM turns abstract transactions into cards, connectors and slots

The Card Electromechanical Specification sets card dimensions, connectors, lanes, presence signals and power rules. It allows designers to target a recognised slot rather than a single chassis.

AI accelerators strain that envelope. The most demanding cards need auxiliary power, large heatsinks, liquid cooling or proprietary carriers. PCI-SIG can revise connectors and form factors, but it cannot repeal thermodynamics. CEM maintains a broad common market; extreme systems can move beyond the conventional card.

Form-factor specifications take PCIe into storage, embedded systems and specialised modules

PCIe is not limited to the full-height card. There are compact modules, storage form factors, embedded devices and specific assemblies. Each defines envelope, connector, lanes, power and service.

The diversity allows protocol, drivers and software to be reused. It also adds complexity: a storage module and a rack accelerator can share transactions, but have different installation, cooling and replacement. PCI-SIG coordinates the common layer; the builder decides the physical form.

Operating-system support turns a specification into an economic platform

The interface becomes a market when operating systems already know how to discover devices, allocate resources, report errors and load drivers. Decades of PCI and PCIe support reduce the cost of introducing a NIC, a storage controller or an accelerator.

That base also limits change. A capability in the standard can remain unused until the kernel, hypervisor and tools expose it. Cloud operators pin versions for stability. PCI-SIG preserves the model; the deployment schedule belongs to software maintainers and platform owners.

Cables extend distance and add another boundary to qualify

Board traces become difficult at high speeds. Internal or external cables let connectors, storage or accelerators move beyond the motherboard and enable serviceable or composable designs.

A cable adds loss, reflections and mechanical cycles. Manufacturing, bend and temperature matter, and retimers may be needed. A compliant cable can still be integrated into a full channel that is out of budget. Rules reduce uncertainty; the weakest part still determines the speed.

The optical PCIe work reflects the pressure of rack scale, not a finished model

Copper loses reach and consumes more as rates rise. AI systems also want to separate accelerators and memory at distances greater than a board. PCI-SIG is studying optics, connectors and architectures that could carry PCIe semantics further.

There is no evidence of a single universal optical architecture already deployed. Optics add modules, control, power, latency, reliability and service. It can complement copper, coexist with Ethernet or remain in specialised systems. The importance lies in the problem being solved, not in a closed result.

PCIe 6.0 changed the signalling model to 64 GT/s

PCIe 6.0 was published in January 2022 and doubled the per-lane rate to 64 GT/s. To achieve this, it adopted PAM4, fixed-size FLIT units, forward error correction and CRC.

The transition required new transmitters, receivers, equalisation, test methods and error protection. Backward compatibility remained, but it was no longer a simple frequency increase. The physical channel and its validation became even more important.

PAM4 doubles the information per symbol and reduces electrical margin

Binary signalling carries one bit per symbol. PAM4 uses four amplitude levels and carries two bits per symbol, raising the rate without doubling the entire fundamental frequency.

The price is less separation between levels. Noise, loss, crosstalk and distortion consume more margin. Receivers and tests become more complex and may require more power. PAM4 shifts the problem to analogue precision, encoding and recovery; it is not a free doubling of performance.

FLIT mode reorganises transactions for a fast, noisier channel

PCIe 6.0 introduced fixed-size FLITs so that FEC and CRC could be applied uniformly. Earlier generations used packets with more variable framing.

The change is almost invisible to the application, but fundamental for controllers, switches, retimers and testing. Everyone must agree on how to packetise, protect, acknowledge and retry. PCI-SIG preserves the software-visible model while changing the machinery underneath.

FEC and CRC reduce errors without making the channel infallible

FEC adds redundancy to correct some errors without waiting for retransmission; CRC detects the remaining corruption. Both allow a noisier environment with more raw errors to be used.

They do not rescue every failure. A burst can exceed correction, firmware can mishandle a state, and a poor channel may fail to train at the target rate. Protection also consumes bits and logic. The operator needs visibility into corrected errors, uncorrectable errors, retries and the negotiated rate.

PCIe 7.0 doubled the per-lane rate again to 128 GT/s

PCI-SIG published PCIe 7.0 in June 2025. It keeps PAM4 and FLIT and raises the rate to 128 GT/s per lane. The organisation describes an x16 link as up to 512 GB/s bidirectional.

The generation targets data centres, HPC, AI, cloud and networking. Commercial reality runs through SerDes IP, switches, retimers, processors, accelerators, test equipment and complete platforms. The final specification is a milestone, not on its own proof of mature products.

PCIe 8.0 is still a draft, not a delivered interface

Draft 0.5 was distributed to members on 1 May 2026. It targets 256 GT/s, explores connectors, aims to maintain latency and reliability, reduce power and preserve backward compatibility. The full specification is planned for 2028.

The status must accompany every claim. The document can guide early architecture, but features and tests can still change. There is no finished PCIe 8.0 compliance programme or broad market. A roadmap is not a deployment.

A terabyte per second is a raw x16 target, not application performance

The target of up to 1 TB/s bidirectional adds both directions and assumes all 16 lanes at the raw rate. It does not mean an application moves a terabyte of useful data every second.

Headers, flow control, FEC, transaction patterns, memory, device engines, switches and software reduce the result. The responsible phrase is 'raw bidirectional interface target'. Any higher claim needs a defined topology, device and benchmark.

Negotiated width and speed preserve function but can hide a weak channel

A link can drop from x16 to x8 or from a recent generation to an older one and remain operational. Degradation aids development and continuity.

It can also hide faults if monitoring only checks device presence. A GPU at half width can pass a simple check and deliver far less performance. Telemetry must record generation, lanes, equalisation and errors, and treat degradation as an explicit state.

Switches turn PCIe into a fabric and introduce oversubscription

A switch connects one or more upstream ports to many downstream devices. It allows more accelerators, NICs and storage to be attached than the processor's direct lanes support, and can enable composable pools.

It does not create bandwidth. Many devices can share a narrower upstream. Latency, ordering and peer-to-peer matter. PCI-SIG defines the behaviour; the architect decides fan-out, oversubscription and redundancy. Simultaneous performance depends on those decisions.

Peer-to-peer traffic can save host work and complicate isolation

Some devices exchange data without passing every transaction through main memory. An accelerator can talk to a NIC or another accelerator and reduce copies and CPU work.

It is not always enabled or safe. Firmware, the IOMMU and control services can restrict it. Devices differ in translation, ordering and resets. The ideal topology for one workload can saturate with another. A performance claim needs to name the path, devices and isolation policy.

Retimers extend channels and create firmware dependencies

A retimer receives a degraded signal, recovers clock and data and retransmits. At modern rates, it enables long paths, connectors and cables in large servers.

It is also an active device with its own firmware and states. It affects training, equalisation, latency, errors and reset. There can be several from different vendors. Diagnosing a link requires knowing a topology that the operating system's simple tree does not always reveal.

Reliability features only matter when the platform exposes their evidence

PCIe includes mechanisms for reporting and managing errors. Advanced Error Reporting can distinguish correctable and fatal events; other mechanisms help contain failures.

The value depends on firmware and visibility. Events can be aggregated, lost or misattributed. An error storm can be destabilising; aggressive recovery can take out a usable device. The operator needs tested policies for logging, thresholds, isolation and replacement.

AI accelerators strain the assumptions about power, cooling and connectors

PCIe was born with cards far less demanding than today's accelerators. Modern equipment uses auxiliary power, large heatsinks, liquid cooling or proprietary baseboards. Many accelerators share switches and retimers with networking and storage.

The interface remains vital for enumeration, configuration, management and a widely supported data path. But the physical product is no longer always a conventional card. PCI-SIG can evolve connectors and cabling; the platform and the data centre solve power and heat.

CXL builds memory semantics on PCIe without becoming PCI-SIG

Compute Express Link uses PCIe physical and electrical foundations and adds protocols for cache coherence and memory access. It reuses drivers, channels and discovery in cases that ordinary PCIe transactions do not cover.

The CXL Consortium governs those semantics. PCI-SIG does not own the coherence, pooling or its software. Shared layers make the organisations interdependent, not subordinate.

UCIe addresses the package boundary that PCI-SIG does not control

Universal Chiplet Interconnect Express defines a short link between dies inside a package. It can carry PCIe and CXL protocols, but its challenges are bumps, interposers, yield, thermals and die testing.

Companies and engineers are present in both consortia, but the mandates are different. PCI-SIG controls PCI Express; the UCIe Consortium controls the chiplet link. Protocols can be reused across new boundaries without a single institution governing all of them.

Ethernet and proprietary fabrics compete for accelerator traffic

AI systems use several interconnects. PCIe connects host and devices; Ethernet scales between racks; proprietary fabrics optimise specific relationships; CXL provides coherent memory.

The PCIe roadmap preserves a large ecosystem, but does not guarantee that it carries every critical byte. It is likely to remain the universal path for discovery, control and compatibility while other networks carry certain high-volume workloads. The evidence supports coexistence, not a single winner.

Virtualisation turns one physical endpoint into many policy boundaries

SR-IOV lets a physical device expose virtual functions for several machines or workloads. Other models try to share devices at larger scale.

The interface does not guarantee isolation. Firmware, IOMMU, hypervisor, driver and orchestrator all play a part. Pressure from one function can affect another, and a reset can cover more than expected. PCI-SIG defines the representation; the operator must demonstrate security and availability.

Security entered the interconnect with Integrity and Data Encryption

IDE protects certain Transaction Layer Packets against observation, modification and replay. It matters when the link crosses switches, retimers, cables or shared infrastructure.

The feature depends on endpoints, keys and configuration. It adds state that must be diagnosed and can complicate some observations. It reduces a specific surface; it does not automatically make the device, driver, firmware or platform trustworthy.

DOE and SPDM give security messages a common path over PCIe

Data Entity Exchange offers a mailbox-style transport for structured entities. It can carry SPDM-related exchanges to discover capabilities, authenticate, obtain measurements and prepare keys.

The transport does not define all trust. Certificates, revocation, interpretation of measurements, manufacturing and updates are outside it. PCI-SIG standardises the path; DMTF, vendors and the platform provide the rest. A successful exchange does not certify the whole chain.

TDISP helps isolate device interfaces in trusted systems

The Trusted Device Interface Security Protocol supports assigning an interface to a trusted execution environment. The system must know which interface is delivered, in what state and how it is isolated from the rest.

TDISP depends on discovery, authentication, IOMMU, hypervisor, firmware and roots of trust. A correct protocol does not prove that internal firmware is free of malware. It is a standardised piece, not a total device certification.

Link protection does not certify firmware or the supply chain

IDE can protect traffic in transit and TDISP can help with isolation. Neither reviews all firmware, validates every manufacturing component or replaces vulnerability management.

Complete trust requires identity, certificates, keys, updates, isolation and recovery. A compromised endpoint can emit harmful but correctly encrypted traffic. PCI-SIG makes parts of trust interoperable; final responsibility remains distributed.

Compliance workshops turn prose into a limited test matrix

A coherent specification can still be interpreted differently. Workshops bring products and measurement equipment together to test electricals, protocol and interoperability. Failures can lead to fixes in product, procedure or text.

Passing means a device met a defined set under named conditions. The event does not reproduce every board, BIOS, switch, cable, temperature and workload. It is strong evidence within its scope, not a universal guarantee.

Test equipment and fixtures form an invisible supply chain

Compliance at high speed requires oscilloscopes, BERTs, analysers, reference boards, cables, fixtures and software. Those tools are designed while the standard is still changing, so their suppliers are part of the ecosystem.

A delay in fixtures can delay the market. At 128 or 256 GT/s, small differences in probes, connectors or de-embedding change the measurement. A generation becomes commercially real when it can be manufactured and measured repeatably.

Authorised test labs expand access to recognised testing

The Authorised Test Lab programme lets third parties run defined testing under PCI-SIG rules. It offers another route when timing, geography or the product cycle does not fit a workshop.

The lab's authority depends on generation, programme and fixtures. Passing protocol does not remove an electrical platform defect. The lab expands access; it does not replace internal validation or operator qualification.

The cost of compliance grows with speed and can decide who enters the market

Each generation requires new SerDes, modelling, lab time, fixtures and expertise. A large vendor can test many prototypes; a small one may have a single chance before its window closes.

Formal testing can also help small vendors by offering a recognised signal. The structural problem is that physics makes evidence expensive. Regional labs and training reduce barriers, without removing the advantage of those who can pay for several iterations.

The Integrators List records completion of testing, not universal compatibility

Products that pass the relevant requirements can appear on the Integrators List. It is a useful signal that a card, controller or system completed a process at a given time.

It does not mean every listed item has been combined with every host. Firmware changes and a topology can bring together parts never tested together. The list reduces uncertainty, but purchasing must still include platform and fleet qualification.

Brand policy disciplines claims without guaranteeing quality

PCI-SIG controls the PCI and PCI Express marks. The rules help prevent any vendor from using the name without accepting membership and testing conditions, preserving the value of the common language.

A logo does not guarantee latency, application performance, firmware security or service life. It is a claim within a scope. The mark improves the honesty of advertising; the buyer must understand what it means.

Multi-vendor servers show the gap between component testing and platform testing

An AI server combines a root complex, switches, retimers, accelerators, NICs and storage. Each component may have passed its tests while the exact combination has never been exercised.

Failures appear in reset, peer-to-peer, bifurcation, permissions, firmware and thermals. Component compliance narrows the search, but full integration remains another discipline. The more modular the system, the more necessary complete-topology testing becomes.

Operators need topology, firmware and error telemetry to diagnose

Traditional inventory sees the endpoint and can hide switches, retimers and cables. When a link drops in rate or produces errors, the operator needs the path, the negotiated state, versions and counters.

PCI-SIG defines mechanisms; the manufacturer decides what is exposed to the fleet. Operators should record generation, width, errors, resets and firmware. A common interface loses value if diagnosis remains proprietary.

Conferences turn private drafts into shared implementation knowledge

Developer Conferences and meetings in different regions explain generations, compliance, security, form factors and practical lessons. They reduce isolated interpretation of dense documents.

Presentations are not normative and a demo does not prove universal production. Their value lies in tacit knowledge: questions, examples and experiences that do not fully fit in a specification.

AI infrastructure makes PCI-SIG both more central and more limited

Accelerator density raises the value of a common link and the ability to mix vendors. Software support and compatibility make PCIe especially relevant.

The same market exposes boundaries: power, optics, coherent memory, chiplets and specialised fabrics belong to other bodies and vendors. PCI-SIG is more central because many components enter through PCIe, and more limited because the highest-performance system is a federation of interfaces.

AI workload scheduling depends on the topology hidden under a server name

A scheduler can see several identical accelerators even when they sit behind different switches, share upstreams or are close to different CPU sockets. That topology affects data movement, collectives, storage and networking.

The platform can expose locality, but not always completely or portably. A neighbour-to-neighbour benchmark does not represent a job crossing a saturated switch. PCIe topology becomes an input to scheduling economics.

The absence of audited accounts limits analysis of institutional resources

Continuity is visible in three decades, recurring events, more than a thousand members and an active roadmap. There is no audited public breakdown of revenue, reserves, staff or spending by group.

The gap matters because specifications, legal counsel, fixtures, workshops, branding and education require resources. It also prevents knowing how much the institution depends on a few large companies. The evidence shows continuity, not a detailed financial picture.

Supply-chain resilience requires replaceable implementations, not just a common standard

A common interface lets different vendors build controllers, switches, retimers and devices. That diversity helps when a factory fails, a product is withdrawn or trade rules change.

Replacement is not automatic. Firmware, management, power consumption and failure modes vary; qualification data may belong to the original vendor. The standard creates the possibility of replacement. Organisations preserve it with alternative sources, portable diagnostics and advance qualification.

A global interface does not remove the geography of the supply chain

A controller's IP can be designed in one country, manufactured in another, packaged in a third and assembled into a server for yet another market. Conferences and labs help coordinate that chain.

Export controls, manufacturing concentration, language and unequal access to equipment and early silicon do not disappear. The grammar is global; the ability to manufacture the newest generations remains embedded in a geographically uneven semiconductor economy.

Private standards governance has public-infrastructure consequences

Specifications are developed among private members, but their effects reach clouds, hospitals, universities, banking and government. A connector or security decision affects global chains; the draft schedule influences who reaches the market.

Private standardisation can be faster and more specialised than regulation, but it raises questions of access, representation and transparency. There is no evidence of misconduct in the file. The legitimate question is who participates early, which constraints are heard and how trade-offs are explained to users who will never be members.

PCI-SIG's enduring achievement is controlled evolution, not total control

The organisation has kept an architecture relevant while signalling, form factors, security and uses changed. It moved from PCI to a serial fabric across graphics, storage, networking, cloud and AI.

It does not therefore own modern computing. It does not guarantee every platform, does not direct neighbouring standards and does not decide every accelerator path. It provides language, a change process and bounded testing. In a machine made of rival parts, that limited form of governance is precisely its value.