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Home » Synopsys introduces hardware-assisted chip verification
Engineers-testing-semiconductor-chip-designs-using-simulation-software
Engineers-testing-semiconductor-chip-designs-using-simulation-software
IT Infrastructure

Synopsys introduces hardware-assisted chip verification

By Debbie WangMarch 12, 2026No Comments3 Mins Read
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  • Synopsys has introduced a software-defined, hardware-assisted verification system designed to accelerate AI chip development.
  • The approach aims to help semiconductor companies validate complex processors more efficiently as AI workloads expand.

What Happened

Chip design software company Synopsys has announced a new verification approach intended to support the growing demand for artificial intelligence hardware. The company is introducing software-defined, hardware-assisted verification to help developers test and validate increasingly complex chip architectures.

Verification is a critical stage in semiconductor design. Engineers must ensure that a chip behaves exactly as intended before it reaches manufacturing. This process becomes more difficult as processors grow more sophisticated, especially those designed for AI workloads.

Synopsys said its new system combines software-based verification tools with specialized hardware acceleration. The goal is to allow engineers to run large-scale simulations and identify potential problems earlier in the design process.

Artificial intelligence applications have added new pressure to chip development cycles. AI processors often require specialized architectures and extremely high performance, which can increase design complexity.

Companies developing AI chips—from start-ups to major technology firms—must therefore test vast numbers of scenarios before committing to fabrication. Any flaw discovered after manufacturing can lead to costly delays.

Synopsys positions the new verification approach as a way to streamline this process. By integrating software and hardware testing capabilities, the company says chip designers could scale verification workloads more effectively.

Also Read: https://btw.media/all/it-infrastructure/nexperia-china-claims-12-inch-wafer-chip-production/

Why It’s Important

The announcement highlights a key challenge facing the semiconductor industry. As artificial intelligence expands, chip architectures are becoming more specialized and complicated. This increases the risk of design errors and lengthens development cycles.

Verification already accounts for a large share of chip development time and cost. Tools that accelerate testing could therefore play an important role in supporting the broader AI ecosystem.

However, the benefits of new verification technologies will depend on how widely they are adopted. Semiconductor design flows are complex, and companies often rely on established tools and processes.

There is also the broader issue of the rapidly growing demand for AI chips. Technology companies, cloud providers, and research organizations are all racing to build new processors capable of handling machine learning workloads.

If verification tools cannot keep pace with this demand, chip development could become a bottleneck in the AI supply chain.

Synopsys’ new approach reflects the industry’s attempt to address that risk. Yet it also underscores a deeper reality: the infrastructure behind artificial intelligence—from chip design to manufacturing—remains highly complex and capital-intensive.

Also Read: https://btw.media/all/it-infrastructure/global-data-centre-investment-set-to-soar-to-3t/

Chip Verification EDA hardware Synopsys
Debbie Wang

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